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In a synchronous network digital payload data is carried at a particular clock frequency within a synchronous message format. This payload data may include both asynchronous digital data and synchronous digital data originating at a different data rate in a foreign digital network. The Synchronous Optical Network (SONET) and its European counterpart the Synchronous Digital Hierarchy (SDH) provide a standard format of transporting digital signals having various data rates, such as a DS-0, DS-1, DS-1C, DS-2, or a DS-3 signal and their European counterparts within a Synchronous Payload Envelope (SPE), or a container that is a part of a SONET/SDH STS-N/STM-N message frame. In addition to the digital data that is mapped and framed within the SPE or container, the STS-N/STM-N message frame also includes overhead data that provides for coordination between various network elements.
If the digital data that is mapped and framed in the STS-N/STM-N message was originally carried by a clock signal having a different frequency than the SONET/SDH line rate clock, certain adjustments to the framed digital data must be made. For example, if a DS-3 data signal carried by a 44.763 MHz clock signal is to be carried in a fiber-optic network by mapping the DS-3 signal into the SPE of an STS-1 message, extra bits must be added to the DS-3 signal prior to transmission through the SONET/SDH network. These extra bits are commonly referred to as stuff bits or gap bits and are merely place markers and carry no valid data. These gap bits are required because the DS-3 signal is slower than the SONET/SDH clock frequency, and hence there are not enough DS-3 bits at the higher frequency to form a complete SONET frame.
When the STS-1 message is received at the exit node, the overhead bytes must be removed from the SONET STS-1 message. The payload data that remains is de-framed and de-mapped into a serial data stream carried by a higher clock frequency than the nominal clock frequency of the payload data. In addition, the recovered data still contains the inserted gap data bits. If, for example, DS-3 data has been transported via a SONET/SDH network, the DS-3 data must be converted from the SONET clock signal to the lower frequency DS-3 clock signal and the gap data bits must be removed prior to the DS-3 signal being B3ZS-encoded for electrical re-transmission.
To transfer data from one clock domain to another, for example from the DS-3 embedded within the SONET signal rate to the proper DS-3 signal rate, typically a desynchronizer is used to provide a buffering mechanism between the clock signals. A desynchronizer typically includes an elastic store buffer that can be a first-in-first-out memory that receives gapped data recovered from a synchronized data payload as an input at one clock frequency and stores the data in appropriate storage locations. Data is read from the elastic store buffer at a different clock frequency and is provided as output data at that frequency. This output data does not contain the gap data bits that were added when the slower signal was mapped into the faster SONET/SDH STS-1 message.
Once the data has been de-mapped and de-framed from the SPE and the gaps removed, a phase locked loop (PLL) is typically used to recover the clock information and to adjust the read signal associated with the data stored in the elastic store for transmission downstream of a smooth data clock signal carrying a smooth data signal.
Although the SONET/SDH fiber optic network is a synchronous network, variations in clock signals across the network may occur. These variations in clock signals between various network elements may cause a loss of data downstream from the sender if the clock signal at which data was written to the synchronous signal and the clock signal at which the data was read from the synchronous payload are sufficiently different. A variety of conditions can cause variations in clock signals. For example, network clock instability, electrical noise and interference, effective changes in the length of transmission media, changes in the velocity of propagation, Doppler shifts, and irregular timing information and other electrical and network problems may all cause clock variations.
To mitigate the problems caused by clock variations across a network, the SONET/SDH STS-N/STM-N messages are provided with a pointer adjustment mechanism within the transmission overhead bytes that allow for some movement of the data within the SPE. The pointer adjustment mechanism includes a pair of bytes, H1 and H2, that identify the start of the next SONET/SDH payload byte and also indicate if the pointer adjustment byte, H3, is to be used. The third overhead byte, H3, provides for active pointer adjustment when a negative justification of the SPE is required. Positive justification involves marking the byte of after the H3 byte as a dummy or stuff byte, or as valid data. These pointer adjustments, which occur in the H1 and H2 transmission overhead bytes, allow for up to eight (8) bits of data to be added to a SONET/SDH message frame (using the H3 overhead byte) or for up to eight (8) bits to be removed from the frame. This allows for the SPE/container to be re-framed and re-synched at a network node that has a slightly different network clock. Thus, in addition to the gap data necessary to compensate for payload data that is carried by a different frequency clock signal, up to eight bits of data may be added or removed at each network element in the network due to clock instability in the network.
During a pointer adjustment, which may be also known as a pointer movement, the H1, H2, and H3 bytes may either add or deplete eight (8) bits to/from the recovered data signal at one time. Pointer adjustments can be periodic or aperiodic in nature. A periodic pointer adjustment may be caused, for example, when the SPE transporting the data has a constant clock offset at the output node of the network relative to the input node. An aperiodic or non-periodic pointer adjustment may be bursty in nature when caused by a transient problem or condition within the network.
Although the synchronous system may adjust the payload data using pointer adjustments to account for clock and phase variations, the clock and phase shifts caused by the pointer adjustments and/or the de-gapping of the payload data can affect the output rate of the data clock provided by the PLL. Typically, clock and phase shifts have two components. One is a high frequency jitter component that is classified as a clock or phase shift that is greater than 10 Hz. A second is a low frequency wander component that is classified as a clock or phase shift that is less than 10 Hz.
Jitter refers to the phase variations in the clock signal, which may cause errors in identifying bit positions and values accurately, and is therefore an issue in synchronous systems. Wander refers to phase variations that typically affect the frame and time-slot synchronization. Each network element adds some amount of noise to the SPE that eventually contributes to the timing instability in the form of jitter and wander in the recovered payload signal.
As is known, the PLL used to recover the smooth clock signal and smooth data signal is able to smooth out some phase jumps caused by pointer adjustments or asynchronous stuff bits. A PLL is most effective at filtering out high frequency jitter components, i.e., those with a frequency greater than 10 Hz., but is not effective at filtering out the low frequency wander components. Since, typically the wander components are much less than 10 Hz. these wander components are well within the bandwidth of the PLL and are passed without being attenuated. To construct a PLL with a small enough bandwidth to filter the wander components of the phase jumps, large time constants in the PLL control loops would require large component values for the resistors and capacitors used in the PLL. In addition, the large time constants required would result in a PLL that is slow to lock onto the reference signal and would cause long delays in recovering lock after a transient event.
One source of jitter and wander errors in the output data rate can be caused by the pointer adjustments within the synchronous signals. Each pointer adjustment signal or asynchronous gap data results in a data gap for a given number of clock cycles.
If the input data rate and/or the output data rate to and from the elastic store change by too large a value, it is possible that the elastic store can experience a data overflow condition or a data underflow condition. Data overflow occurs when data is written to the elastic store at a faster rate than usual, or read at a slower rate than usual, causing the elastic store to accumulate data faster than data is read from it. The elastic store will be unable to store all of the incoming data, and data will be lost. Similarly, data underflow occurs when data is written to the elastic store at a slower rate than usual, or read at a faster rate than usual, causing the elastic store to lose data. In this circumstance, undefined and unknown data will be read from the elastic store.
Typically, the elastic store used in the desynchronizer will have a write/read control system that attempts to maintain the output data rate at a specified rate, and maintain the elastic store at a predetermined fill level. If the elastic store begins to overfill, that is more data is being written into the elastic store than is being read from it, the elastic store may overflow and lose data. The write/read control system will increase the data output rate of the elastic store until the proper storage level in the elastic store is reached. Once the proper storage level is reached, the write/read control system will decrease the data output rate. If the elastic store begins to underfill, that is less data is being written into the elastic store than is being read from it, the elastic store may underflow and provide output data that is extraneous and undefined. The write/read control system will decrease the data output rate of the elastic store until the proper storage level in the elastic store is reached. Once the proper level is reached, the write/read control system will increase the data output rate.
When a pointer adjustment is received however, there may up to eight (8) bits that are added to the elastic store or skipped and not written to the elastic store. The inconsistent nature of the gapped data can result in large changes in the data output rate. Typically, pointer adjustments are resolved by xe2x80x9cleakingxe2x80x9d bits from the elastic store at a predetermined rate over a predetermined period of time. Leaking the bits one at a time prevents the excess bits from the pointer adjustment from negatively affecting the output data rate. Yet, as noted above, pointer adjustments may occur either periodically or non-periodically. A constant xe2x80x9cbit leakingxe2x80x9d rate is unable to adequately leak bits to cover a wide range of periodic pointer adjustments or bursty non-periodic pointer adjustments. If sporadic pointer bursts occur on top of the periodic pointer adjustments due to transient effects or if multiple pointer adjustments occur in a bursty fashion the fixed xe2x80x9cbit leakxe2x80x9d rate would be unable to respond and overflow or underflow of the elastic store may occur.
Thus it would be advantageous for a desynchronizer that is able to provide an output data rate of the extracted data having reduced jitter and wander and be able to adapt the output data rate to a plurality of pointer adjustments without sacrificing data integrity.
An apparatus and a method for a desynchronizer for smoothing a gapped data signal and a gap clock signal extracted from a synchronous message is disclosed. A gap regulator module re-maps the gapped data signal into another frame format in which the gaps in the data are uniformly distributed throughout the gapped data signal. A pointer leak logic module determines the bit leak rate as a function of received increment and decrement pointer adjustment signals. The pointer leak logic module adaptively determines the bit leak rate using at least two separate algorithms. In one case, if the increment and decrement pointer adjustment signals are periodic in nature, the bit leak rate is determined by dividing the periodic rate interval between two successive pointer adjustment signals by eight (8). In a second case in which the pointer adjustment signals are not periodic in nature, an exponential bit leak rate is used that is a function of the number of pointer adjustment signals that have been received. The pointer leak logic module provides a uniformly gapped data signal that has been adjusted by bit leaking to a phase locked loop that provides a smooth output data signal and extracts a smooth output clock signal therefrom.
In one aspect, the gap regulator comprises a first-in-first out memory that is coupled to the gapped data signal and the gapped clock signal. A write address counter is coupled to the gapped clock signal and provides a write address pointer that is used by the first-in-first-out memory to store the incoming data. A read address counter is coupled to the reference clock signal and provides a read address pointer that is used to provide the address that data is output from the first-in-first-out memory. An address comparator receives the write address pointer and the read address pointer and is configured and arranged to provide a FIFO fill indicator signal as a function of the difference between the write address pointer and the read address pointer. A B-frame generator receives the FIFO fill signal and the reference clock signal and is configured and arranged to provide the plurality of new gap data position indicators and to indicate via the stuff bit position indicator if the clock cycle corresponding to the stuff bit is to be skipped. The read counter is coupled to the B-frame generator and is configured and arranged to skip a a clock cycle corresponding to one of the plurality of gap position indicators and to skip the clock cycle corresponding to the stuff bit when the stuff bit indicator indicates that the bit corresponding to that clock cycle is not a data bit, and to read the address corresponding to that instant when the stuff bit indicator indicates that the clock cycle of that indicator should contain valid data.
The B-frame generator includes a counter coupled to the reference clock signal that provides a reference clock count signal of the reference clock signal, and a gap indicator logic module coupled to the reference clock count signal and the FIFO fill indicator signal. The gap indicator logic module is configured and arranged to remap the plurality of gapped data contained in first-in-first-out memory into a B frame-format and to provide as an output a plurality of data in the B-frame format and a plurality of gap position indicators corresponding to the reference clock positions to be skipped from reading the first-in-first-out memory. In addition, the B-frame generator provides a stuff bit indicator that is indicative of a specific instant in the frame and an indicator if the data at that instant in the frame is a stuff bit or a data bit.
A B-frame includes 25 data sets of data, wherein each set of data includes 20 data subsets of data, and each subset of data includes 10 data bits of data. Within the data subsets of data, bit ten of every subset of data is a gapped bit; bit five of data subset twenty of every data set of data is a gapped bit; bit five of data subset ten of data set twelve is a gapped bit; and bit five of data subset ten of data set twenty-four is a stuff opportunity bit. Indicia is provided indicating whether the stuff opportunity bit is a valid data bit as determined by the gap indicator logic.
In another aspect, the pointer leak module includes a pointer leak write address counter that is coupled to the reference clock signal and to the plurality of gap position indicators and the stuff bit position indicator. The pointer leak write address counter is configured and arranged to provide an elastic store write address. An elastic buffer having a plurality of storage locations, receives the uniformly gapped data signal that includes a plurality of uniformly gapped data, the reference clock signal, and the elastic store write address. The elastic store is configured and arranged to write the received plurality of uniformly gapped data to one of the plurality of storage locations corresponding to the elastic store write address in accordance with the reference signal clock. A pointer offset and leak module receives the increment and decrement pointer adjustment signals and one of the plurality of gap position indicators. The pointer offset and leak module is configured and arranged to determine the periodicity or non-periodicity of the intervals between a plurality of occurrences of the increment and decrement pointer adjustment signals, and to determine a pointer offset value as a function of the plurality of occurrences of the increment and decrement pointer adjustment signals. The pointer offset and leak module provides as outputs a periodic interval signal containing indicia of whether the plurality of occurrences of the increment and decrement pointer adjustment signals are periodic and if so, a value of the periodicity, and the pointer offset value. A leak rate calculator module, receives the reference signal clock, the pointer offset value and the periodic interval signal and one of the plurality of gap position indicators. The leak rate calculator module is configured and arranged to determine a bit leak rate as a function of the pointer offset value and the periodic interval signal. The leak rate calculator module determines the bit leak as a function of a non-periodic plurality of occurrences or as a function of a periodic plurality of occurrences, the leak rate calculator module providing as an output a bit leak event signal. The pointer offset and leaking module receives the bit leak event signal and is configured and arranged to adjust the pointer offset value so as to reduce the magnitude of the pointer offset value by one for each bit leak event signal received. A pointer leak read address counter is coupled to the elastic store, to the reference clock signal and to the plurality of gap position indicators and the stuff bit indicator. The pointer leak read address counter is configured and arranged to provide as an output a read pointer address. A phase detector module receiving the elastic store write address, the elastic store read address, and the pointer offset value. The phase detector module is configured and arranged to determine the stuff bit control value, wherein the stuff bit control value indicates if the bit occupying the stuff opportunity bit position is a valid data bit or a stuff bit. In the event that the bit occupying the stuff opportunity bit position is a valid data bit, that data bit is read from the elastic store, otherwise, that data bit is a stuff bit and is skipped. The pointer leak read address counter receives the stuff bit control value and is configured and arranged to adjust the read pointer address as a function of the stuff bit control value. The elastic store is configured and arranged to read the data stored at the storage locations corresponding to the received read address pointer and to provide a uniformly gapped data signal containing a plurality of uniformly gapped data.